MAE Seminar: Chemical Patterning Technologies for Scaling IC Manufacturing Beyond the Reach of Optical Lithography
Abstract: Optical lithography has been the cornerstone of IC manufacturing since the days integrated circuits were invented. It has supported scaling of transistors in line with Moore's law (transistor density in ICs doubles about every two years) through generations of IC manufacturing. However, as we continue to shrink the critical dimensions on ICs, high volume manufacturing cannot rely solely on photolithography to support the scaling needs of the industry. This is due to the state-of-the-art DUV 193nm immersion lithography already reaching its resolution limits with respect to future IC nodes. No single-pass lithographic technique in existence today has the ability to define the critical dimensions necessary to support scaling below 5nm node. Chemical patterning technologies (CPTs) hold great promise to enable continued scaling without the constraints of lithographic resolution in a cost effective way. It can utilize the already established high volume manufacturing capabilities of conventional optical lithography tools and combine it with bottom-up additive manufacturing using molecular design and fabrication. CPTs for IC manufacturing are primarily divided into directed self assembly (DSA) and chemical selective deposition. DSA has attracted a lot of attention from the IC manufacturing industry due to its versatility with patterning structures and pitch as well as compatibility with existing tool sets. DSA can enable 1D sub 50nm single-pass grating-pitch multiplication not possible with direct lithography or existing pitch multiplication schemes. It can also be utilized for 2D contact holes for CD uniformity and side wall roughness. Such process schemes, their advantages over conventional patterning techniques and the challenges in their high volume manufacturing implementation will be the primary topics of this talk. This will be followed by some discussion on the use of chemical selective deposition techniques in 2D patterning.
Bio: Gobind Bisht is a litho staff engineer in Portland Technology Development at Intel Corporation, Hillsboro, where he started his career in 2012. His primary focus at Intel is on development of next-generation patterning technologies for high volume manufacturing of integrated chips (IC). He also supports factory automation solutions for lithography tools to improve fab efficiency and output. Bisht received his master's degree and doctorate in advanced carbon micro/nano-manufacturing technologies for sensor and biofuel cell applications in 2012 from UC Irvine where he worked in Professor Marc Madou's lab. Prior to Intel, Bisht consulted for several biomedical startups in the field of biomedical sensors. He also holds several patents and publications in the areas of micro/nano-manufacturing for biomedical and IC applications. Bisht enjoys reading, traveling, hiking and playing ping-pong in his free time.