Parallel LDPC Decoding on NoC-based Multiprocessor Platform

Featuring Wen-Hsiang Hu
Ph.D. Candidate
Department of Electrical Engineering and Computer Science
The Henry Samueli School of Engineering, UC Irvine

Location:  2430 Engineering Hall
Free and open to the public

Abstract:
Low Density Parity Check (LDPC) code is an error correction code that can achieve performance close to Shannon limit and inherently suitable for parallel implementation. It has been widely adopted in various communication standards such as DVB-S2, WiMAX, and Wi-Fi. However, the irregular message exchange pattern is a major challenge in LDPC decoder implementation. In addition, faced with an era that diverse applications are integrated in a single system, a flexible, scalable, efficient and cost-effective implementation of LDPC decoder is highly preferable. In this talk, we will present a multiprocessor platform based on Network-on-Chip (NoC) interconnect as a solution to these problems. By using a distributed and cooperative way for LDPC decoding, the memory bottleneck, commonly seen in LDPC decoder design, is eliminated. Moreover, we used a mapping algorithm based on graph spectral clustering to reduce the heavy message exchange among processors during the decoding process. Our approach has successfully decreased the amount of inter-processor communication by 33~52% and 17~46% in a 16-processor and 64-processor environment, respectively. Simulation results from various LDPC codes show good scalability and speedups are obtained by our approach.

About the Speaker:
Wen-Hsiang Hu is currently a Ph.D. student in the Department of Electrical Engineering and Computer Science in The Henry Samueli School of Engineering at the University of California, Irvine. He received his B.S. and M.S. degrees in computer science from National Chiao-Tung University, Taiwan, in 1999 and 2001, respectively. From 2001 to 2006, he was an assistant researcher at National Chip Implementation Center, Hsinchu, Taiwan. His research interests include network-on-chip architecture, parallel processing and system-on-chip design methodology. He is a student member of the Institute of Electrical and Electronics Engineers (IEEE).