A Low Power 10 GS/s 5 bit ADC in 0.13um CMOS Technology

CPCC SEMINAR

Featuring Darya Mohtashemi
Ph.D. Candidate
Department of Electrical Engineering and Computer Science
The Henry Samueli School of Engineering, UC Irvine

Location:  2430 Engineering Hall
Free and open to the public

Abstract:
In high-speed data communication systems with bit rates of 10Gb/s and higher, some form of channel equalization is required to ensure error free data transmission. Digital equalization has been shown to have favorable performance over more conventional analog techniques, therefore, high-speed ADCs are becoming fundamental components of high-speed communication systems. The bottleneck in such systems has been the design of the ADC with reasonable power dissipation. This talk focuses on the challenges of designing a low power 10GS/s flash ADC in 0.13um CMOS and the high-speed design techniques used in the development of this A/D converter.

About the Speaker:
Darya Mohtashemi received a B.S. degree in electrical engineering from K. N. Toosi University of Technology in Tehran, Iran, in 2004, and an M.S. degree in electrical engineering from the University of California, Irvine, in 2006. She is currently pursuing  her Ph.D. degree at the University of California, Irvine. Her research interests include the design of high-speed analog/mixed-signal integrated circuits for optical communications with a focus on high-speed ADC design. She has held two summer internships at ClariPhy Communications, Inc., where she was an analog IC design engineer intern. Mohtashemi received the UC Irvine Henry Samueli Endowed Fellowship in 2006. She is a student member of the Institute of Electrical and Electronics Engineers (IEEE). 

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