EECS Seminar: Toward Hardware Cybersecurity

Abstract: Electronic system security, trust and reliability has become an increasingly critical area of concern for modern society. Secure hardware systems, platforms, as well as supply chains are critical to industry and government sectors such as national defense, healthcare, transportation and financial. Traditionally, authenticity and integrity of data have been protected with various security protocol at the software level with the underlying hardware assumed to be secure and reliable. This assumption however is no longer true with an increasing number of attacks reported on the hardware. Counterfeiting electronic components, inserting hardware trojans and cloning integrated circuits are just a few out of many malicious byproducts of hardware vulnerabilities, which need to be urgently addressed.

In the first part of this talk, I will address the security and vulnerability challenges in the horizontal integrated hardware development process. I will then present the concept of hybrid spin-transfer torque CMOS look-up table-based design, which is our latest effort in developing a cost-effective solution to prevent physical reverse engineering attacks. In the second part of my talk, I will present how information at the hardware level can be used to address some of the major challenges of software security vulnerabilities monitoring and detection methods. I will first discuss these challenges and will then show how the use of data at the hardware architecture level in combination with an effective machine learning-based predictor helps protect systems against various classes of hardware vulnerability attacks. I will conclude the talk by emphasizing the importance of this emerging area and proposing a research agenda for the future.

Bio: Houman Homayoun is an assistant professor in the Department of Electrical and Computer Engineering at George Mason University. He also holds a courtesy appointment with the Department of Computer Science as well as the Information Science and Technology Department. He is the director of GMU’s Accelerated, Secure, and Energy-Efficient Computing Laboratory (ASEEC). Prior to joining GMU, Houman spent two years at UC San Diego, as an NSF Computing Innovation (CI) Fellow awarded by the CRA-CCC. Houman graduated in 2010 from UC Irvine with a doctorate in computer science. He was a recipient of the four-year UC Irvine computer science department chair fellowship. Houman received his master's degree in computer engineering in 2005 from University of Victoria and a bachelor's degree in electrical engineering in 2003 from Sharif University of Technology. Houman conducts research in hardware security and trust, big data computing, and heterogeneous computing, where he has published more than 80 technical papers in prestigious conferences and journals on the subject. Since 2012, he had led 10 research projects, a total of $7.2 million in funding, supported by DARPA, AFRL, NSF, NIST and GM on the topics of hardware security and trust, big data computing, heterogeneous architectures and biomedical computing. Houman received the 2016 GLSVLSI conference best paper award for developing a manycore accelerator for wearable biomedical computing. Since 2017, he has been serving as an associate editor of IEEE Transactions on VLSI. He is currently serving as the technical program co-chair of 2018 GLSVLSI conference.