EECS Seminar: The Era of Accelerators

McDonnell Douglas Engineering Auditorium
Viktor K. Prasanna, Ph.D.

University of Southern California
Electrical Engineering, Computer Engineering Division

Abstract: FPGAs have matured over the years and are being used along with multicore and emerging memory technologies to realize advanced platforms to accelerate a variety of applications. This talk will review the promise of reconfigurable computing leading up to current trends in accelerators. We will illustrate FPGA-based parallel architectures and algorithms for a variety of data analytics kernels in advanced networking, streaming graph processing and machine learning. While demonstrating algorithm-architecture co-design methodology to realize high performance accelerators for deep packet inspection, regular expression matching, packet classification, traffic classification, heavy-hitter detection, etc., we demonstrate the role of modeling and algorithmic optimizations to develop highly efficient IP cores. We also show high-throughput and energy-efficient accelerator designs for a class of graph analytics and machine-learning kernels. Our approach is based on high-level abstractions of the architectures and design of efficient data structures, algorithms and mapping methodologies. We illustrate the performance improvements such accelerators offer and demonstrate the suitability of accelerators for these computations. We conclude by identifying opportunities and challenges in exploiting emerging heterogeneous architectures composed of multicore processors, FPGAs, GPUs and coherent memory.

Bio: Viktor K. Prasanna ( is the Charles Lee Powell Chair in Engineering in the Ming Hsieh Department of Electrical Engineering and professor of computer science at the University of Southern California. He is the director of the Center for Energy Informatics at USC and leads the FPGA ( and Data Science Labs ( His research interests include parallel and distributed systems, including networked sensor systems, embedded systems, configurable architectures and high-performance computing. He served as the Editor-in-Chief of the IEEE Transactions on Computers 2003-06 and is currently the Editor-in-Chief of the Journal of Parallel and Distributed Computing. Prasanna was the founding chair of the IEEE Computer Society Technical Committee on Parallel Processing. He is the steering co-chair of the IEEE International Parallel and Distributed Processing Symposium ( and the steering chair of the IEEE International Conference on High Performance Computing ( A fellow of the IEEE, the ACM and the American Association for Advancement of Science (AAAS), he received the 2009 Outstanding Engineering Alumnus Award from Pennsylvania State University. Prasanna also received the 2015 W. Wallace McDowell award from the IEEE Computer Society for his contributions to reconfigurable computing.